Method and apparatus for reducing power consumption in a computer network without sacrificing performance

ABSTRACT

A method and apparatus for actively managing the overall power consumption of a computer network which includes a plurality of computer systems interconnected to each other. In turn, each computer system has one or more modules. Each computer system of the computer network is capable of independently initiating a transition into a power-conserving mode, i.e., a &#34;sleep&#34; state, while keeping its network interface &#34;alive&#34; and fully operational. Subsequently, each computer system can independently transition back into fully operational state, i.e., an &#34;awake&#34; state, when triggered by either a deterministic or an asynchronous event. As a result, the sleep states of the computer systems are transparent to the computer network. Deterministic events are events triggered internally by a computer system, e.g., an internal timer waking the computer system up at midnight to perform housekeeping chores such as daily tape backups. Conversely, the source of asynchronous events are external in nature and include input/output (I/O) activity. The illusion of the entire network being always fully operational is possible because the system controllers, the interconnects and network interfaces of each computer system remain fully operational while selected modules and peripheral devices are powered down. As a result, each computer system is able to rapidly awake from sleep state in response to stimuli by powering down selected modules thereby accomplishing power conservation without requiring a static shut down of the computer network, i.e., without the overall performance and response of the computer network.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to the field of power management. Moreparticularly, the present invention relates to conserving overall powerin a computer network having a number of computer systems.

2. Description of the Related Art

With the advent of computer systems with high clock speeds and powerhungry peripherals such as hard disk drives, reducing the overall powerconsumption of a computer network which include a large number ofcomputer systems becomes increasingly important as the number ofcomputer systems in the computer network increases and as the capabilityof each of the computer systems increase.

Conventional power conservation techniques for computer systems includepowering down peripheral input/output (I/O) devices such as disk drivesand stopping processor clocks. For example, when an inactivity intervaltimer senses the absence of key strokes on a keyboard within apredetermined time, a signal is sent to the disk drive controller toenter a power saving mode, e.g., to power down the drive motor. Inaddition, the system clock coupled to the processor may be stopped.Subsequently, a user restarts the computer system by depressing a switchwhich causes the disk drive controller to power up the drive motor andrestarts the system clock.

U.S. Pat. No. 4,980,836, issued to Carter et al. discloses abattery-powered portable computer in which a power control logic circuitcontinuously monitors selected peripheral devices such as the keyboard,and in the absence of activity from the selected peripheral deviceswithin a pre-determined interval, stops the system clock and/or turnsperipheral devices such as modems and disk drives off. Subsequently, theuser depresses a standby switch which signals the power control logiccircuit to restore power to the modem and disk drive, and also restartsthe system clock.

Disadvantages of the conventional power conservation methods describedabove include the need for user intervention to reawaken or restart thecomputer system, and the inability of the computer system to process anyincoming data while it is in the power saving mode, i.e, sleeping. Forexample, the Carter computer is unable to automatically power up andestablish a network connection when a network packet arrives at itsnetwork interface, i.e., the modem, because power to the modem isdisconnected when the computer system is in the power saving mode. As aresult, when the Carter computer is powered-down, it also appears to besleeping with respect to its network interface until it is awaken by theuser, e.g., by depressing the keyboard.

Hence there is a need for a transparent method of reducing the overallpower consumption of a computer network which has multiple computersystems coupled together, such that when one or more processors of thecomputer systems in the network enter a sleep mode, the entire computernetwork remains operational, and every processor, including sleepingprocessors, appears to be continuously awake and ready to respond to I/Oactivity, for example to receive an ethernet packet from anothercomputer system in the computer network.

SUMMARY OF THE INVENTION

The present invention provides a method and apparatus for activelymanaging the overall power consumption of a computer network whichincludes a plurality of computer systems interconnected to each other.Each computer system has one or more processor modules and one or moreI/O interface modules. Suitable interconnect(s) for coupling the modulesof each computer system include packet-switched interconnects andcircuit-switched system buses. Suitable network connections for couplingthe computer systems of the network include high speed clusterconnections, local area network (LAN) such as ethernet, and wide areanetwork (WAN) such as asynchronous transfer mode (ATM).

In accordance with the invention, each computer system of the computernetwork is capable of independently initiating a transition into apower-conserving mode, i.e., a "sleep" state, while keeping therespective network interface "alive" and fully operational.Subsequently, each computer system can independently transition backinto a fully operational state, i.e., an "awake" state, when triggeredby either a deterministic or an asynchronous event. As a result, thesleep states of the computer systems are transparent to the computernetwork.

Deterministic events are events triggered internally by a computersystem, e.g., an internal timer waking the computer system up atmidnight to perform housekeeping chores such as daily tape backups.Conversely, the source of asynchronous events are external in nature.Examples of asynchronous events include input/output (I/O) activitycausing a keyboard interrupt from a keyboard controller, and the arrivalof a data packet arriving at a network interface controller of thecomputer system.

In one embodiment, the computer systems are packet-switched and theinterconnects of the computer systems are cross-bar switches. Crossedreference co-pending patent application, entitled "Packet Switched CacheCoherent Multiprocessor System", U.S. patent application Ser. No.08/415,175, filed Mar. 31, 1995, assigned to Sun Microsystems, Inc.provides a detailed description of a patch switch and related packetswitching protocol. A system controller (SC) provides control signalsfor directing the flow of packets through the interconnect in eachcomputer system. Alternatively, the control mechanism provided by the SCcan be distributed, i.e., with the functionality of the SC distributedamong several processor modules. System controllers remains awake whileone or more of their respective modules are powered down.

Upon entering the sleep state, the computer system sets the appropriatestatus/semaphore bits corresponding to its processor module(s).Important data of the processor module(s) including kernel stateinformation is stored in a stable memory. Any cache memory of theprocessor module(s) is flushed into a main memory of the computersystem. Finally, the processor module(s) of the computer system arepowered down. Semaphore bits inhibit power up of processor module(s)when the processor module(s) are executing critical code while in theprocess of being powered down.

As discussed above, the computer system is awaken by either adeterministic or an asynchronous event, the SC receive a wakeupinterrupt request which causes the SC to send a reset signal topowered-down modules. Upon receiving the reset signal, the powered-downmodules execute a power-up sequence. Next, the processor module(s) polla SC status bit to determine the cause of the reset signal. Previouslystored important data is restored if the cause of the reset signal is awakeup interrupt for the computer system as opposed to a system-widepower-on reset. Finally, the status/semaphore bits are cleared toindicate that the processor module(s) of the computer system are nowpowered-up. The computer system is now able to service the cause of theevent.

The power conservation of the computer network results from the abilityof each computer system to appear to be continuously awake whileactually sleeping, thereby contributing to an illusion that the entirecomputer network is continuously "alive" when in fact one or more of itscomputer systems may be in the sleep state. This illusion is possiblebecause the system controllers, the interconnects and network interfacesof each modules remain fully operational while the processor modules andperipheral devices are powered down. Hence the powered down state ofeach processor module is transparent to the other computer systems ofthe computer network.

As a result, the power management of the present inventionadvantageously enables the computer system to rapidly wake up from thesleep state in response to stimuli by powering down selected modulesthereby accomplishing power conservation without requiring a staticshutdown of the computer network, i.e., without affecting the overallperformance and response of the computer network.

DESCRIPTION OF THE DRAWINGS

The objects, features and advantages of the system of the presentinvention will be apparent from the following description in which:

FIG. 1A is a block diagram showing a computer network including multiplecomputer systems coupled to each other for implementing the powermanagement scheme of the present invention.

FIG. 1B shows one of the multi-module computer systems of FIG. 1A.

FIG. 1C, 1D and 1E illustrate exemplary modules, a processor module, anI/O interface module, and a graphics module, respectively, of themulti-module computer system of FIG. 1B.

FIG. 1F shows another one of the multi-module computer systems of FIG.1A.

FIG. 2 is a flow diagram showing a transition of the computer systemfrom an awake state into a sleep state.

FIG. 3A and 3B are flow diagrams illustrating the processing of anasynchronous event and a deterministic event, respectively.

FIG. 3C is a flow diagram showing a transition the computer system fromthe sleep state into the awake state.

FIG. 4 is a block diagram of a four module computer system illustratingreset signals for powering up processor module(s) while preserving thestates of the I/O interface module.

NOTATIONS AND NOMENCLATURE

Asynchronous event: an event triggered externally with respect to thecomputer system.

Deterministic event: events triggered by the computer system, e.g., theexpiration of an internal timer.

Sleep state: a state of the computer system where one or more of itsmodules are powered down.

Awake state: a state of the computer system whereby all its modules arepowered-up.

Wakeup sequence: a sequence executed by the computer system totransition from the sleep state into the awake state.

Power-up sequence: a sequence executed by a module to transition from apowered-down state into a powered-up state.

Power-down sequence: a sequence executed by a module to transition froma powered-up state into a powered-down state.

I/O₁₃ Wakeup₋₋ Enable bit: a control bit in an I/O interface module forinhibiting DMA requests from an I/O bus coupled to the I/O interfacemodule. This bit causes the I/O interface module to issue an interruptrequest (Int₋₋ Req) for a system controller. The system controller thenwakes up the computer system by sending a reset signal to anypowered-down module(s).

S₋₋ Sleep₋₋ Enter and S₋₋ Wakeup₋₋ Enable semaphore bits: the S₋₋Sleep₋₋ Enter semaphore bit of the system controller provides anindicator that the computer system is in the process of entering thesleep state, and inhibits power up of the processor module(s) until thecorresponding S₋₋ Wakeup₋₋ Enable semaphore bit is set. The setting ofthe S₋₋ Wakeup₋₋ Enable bit indicates that the processor module(s) ofthe computer system has completed the power-down sequence and it is nowsafe to initiate a power up of the processor module(s).

Wakeup₋₋ Reset bit: a status bit of the system controller for indicatingthat the cause of reset signal is a wakeup of the computer system, asopposed to a system-wide power on reset.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In the following description, numerous details provide a thoroughunderstanding of the invention. These details include functional blocksand an exemplary computer network to assist a designer in implementingan efficient active power management scheme for the computer networkwhich permits the "sleep" state of the computer system(s) to betransparent to the rest of the computer network. While the powermanagement scheme is illustrated by a specific implementation, theinvention is applicable to a wide variety of network architectures andenvironments. In other instances, well-known circuits, structures andprogram code are not described in detail so as not to obscure theinvention unnecessarily. Accordingly, references to co-pendingapplications are included to provide implementational details which arenot essential for illustrating the principles of the present invention.

In accordance with one embodiment of the present invention, asillustrated by the block diagram of FIG. 1A, a computer network 100 forimplementing the power management scheme includes a local area network(LAN) 192 and a plurality of computer systems 110, 120, . . . 170. LAN192 provides a high speed data link between computer systems 110, 120, .. . 170. As is known to one skilled in the art, computer systems can becoupled to each other by a wide variety of networking topologiesincluding high speed local buses, local area network (LAN) such asethernet, and wide area network (WAN) such as asynchronous transfer mode(ATM), and combinations of the above. In this embodiment, computersystems 110, 120, . . . 170 are similar and hence the followingdescription of computer system 110 is applicable to computer systems120, . . . 170.

Referring now to FIG. 1B, computer system 110 includes a plurality ofmodules 111a, 111b, . . . 111z, an interconnect (IC) 112, a systemcontroller (SC) 114 and a main memory 115. Modules 111a, 111 b, . . .111z are individually coupled to interconnect 112. Main memory 115 isalso coupled to interconnect 112. Control lines couple system controller114 to each of modules 111a, 111b, . . . 111z, interconnect 112, andmain memory 115. The plurality of modules 111a, 111b, . . . 111zincludes one or more processor module(s) and one or more input/output(I/O) interface module(s). Co-pending patent application, entitled"Packet Switched Cache Coherent Multiprocessor System", U.S. patentapplication Ser. No. 08/415,175, filed Mar. 31, 1995, assigned to SunMicrosystems, Inc. provides a detailed description of this embodiment ofcomputer system 110. In this example, module 111a is a processor module,module 111b is an I/O interface module, and module 111z is a graphicsinterface module. Module 111b is coupled to LAN 192 via an I/O bus 116and an I/O controller 118a.

In this implementation, computer system 110 is a packet-switched andinterconnect 112 is a datapath crossbar. Interconnect interfaces ofmodules 111a, 111b, . . . 111z enable the modules to exchange data andcontrol packets with each other via interconnect 112. Although computersystem 110 is packet-switched, i.e., circuit-switched data lines are notrequired, the principles of the invention are also applicable to othernon packet-switched systems. (For detailed information on cachemanagement and data packet transfers by computer system 110 please referto co-pending application co-pending patent application, entitled"Packet Switched Cache Coherent Multiprocessor System", U.S. patentapplication Ser. No. 08/415,175, filed Mar. 31, 1995, assigned to SunMicrosystems, Inc.

FIG. 1C illustrates exemplary processor module 111a of computer system110. Processor module 111a includes an interconnect interface 111a2 andan optional local cache memory 111a1. In this implementation, since theprocessor modules of computer network 100 are similar in structure, adescription of the operation of processor module 111a is equallyapplicable to other processor modules of computer systems 110, 120, . .. 170.

As shown in FIG. 1D, I/O bus 116 couples exemplary I/O interface module111b to I/O controllers 118a, 118b, 118c, 118d of computer system 110.In turn, I/O controllers 118a, 118b, 118c, 118d provide interfaces forLAN 192, SCSI devices such as a hard disk drive 194, a keyboard 196 andan inactivity timer 198. Suitable system buses for implementing I/O bus116 include the SBus and the PCI bus. Although computer system 110 isdescribed as having one I/O interface module 111b, additional I/Ointerface modules can be added to computer system 110 for providingadditional I/O capability, e.g., an ATM connection, an ISDN connectionand a PCMCIA card.

FIG. 1E shows exemplary graphics interface module 111z of computersystem 110. Module 111z is coupled to a graphics display device 195 viagraphics bus 117 and a graphics controller 119. Additional graphicscontroller(s) may be added for supporting additional graphics displaydevices. Graphics controller 119 may also control multiple graphicsdisplay devices.

The power management scheme for computer network 100 of the presentinvention provides processor modules of computer systems 110, 120, . . .170 the ability to transparently enter and leave the sleep state whileLAN 192 remains powered-up, thereby permitting computer network 100 toremain fully operational while reducing overall power consumption. Thisis possible because the respective I/O interface modules of computersystems 110, 120, . . . 170 remain powered-up while one or moreprocessor modules and selected peripheral devices are powered down whencomputer network 100 enter the sleep state; the rationale beingprocessor modules typically consume the most power, along withperipheral devices such as disk drives and display monitors.

In this implementation, while the processor modules may be powered-downindependently, the powered-down modules are powered up by a single resetsignal of computer system 110. In other implementations, separate resetsignals can be used for powering up individual modules.

In accordance with one aspect of the invention, computer system 110enters the sleep state under one of the following exemplary conditions.First, computer system 110 may enter the sleep state whenever itreceives a time-out notification from inactivity timer 198. Variouscriteria can be used by inactivity timer 198, such as inactivity ofkeyboard 196 or inactivity of user process(es) executing on processormodule 111a. Second, computer system 110 can enter the sleep state uponcompletion of specific tasks. For example, processor module 111a caninitiate an entry by computer system 110 into the sleep state uponcompletion of a house-keeping chore such as a periodic memory backup ora chronological task such as user accounting for charge backs. Third, anetwork message may arrive at computer system 110 from a network managervia LAN 192 to computer system 110 initiating an entry into the sleepstate. Fourth, a user at computer system 110 may initiate an entry ofcomputer system 110 into the sleep state by depressing a standby powerswitch. Fifth, a brown-out/power-failure detector of computer system 110may initiate an entry into the sleep state upon detecting an impedingshut-down of the primary power supply of computer system 110. Otherconditions for entering the sleep state are possible since the topologyof computer network 100, particularly computer system 110,advantageously permits both systems designers and end-users a great dealof flexibility in implementing different conditions for entering intothe sleep state.

FIG. 2 is a flow diagram illustrating steps executed by computer system110 to enter the sleep state. First, processor module 111a sets an I/O₋₋Wakeup₋₋ Enable status bit of I/O interface module 111b (step 210). Whenthe I/O₋₋ Wakeup₋₋ Enable bit is set, all direct memory access (DMA)arbitration on the computer's system bus is inhibited, preventing anyDMA to a potentially halted main memory 115. Consequently, any busarbitration request for DMAs will trigger an interrupt request (Int₋₋Req) for powering up processor module 111a. For example, a DMA requestfrom I/O interface module 111b will result in an Int₋₋ Req to systemcontroller 114 for powering up processor module 111a to process the DMA.Thereafter, until the I/O₋₋ Wakeup₋₋ Enable bit has been cleared, systemcontroller 114 is responsible for policing traffic through interconnect112 and for powering-up processor module 111a when the need arises.

Next, an S₋₋ Sleep₋₋ Enter semaphore bit of system controller 114 is set(step 220). Setting the S₋₋ Sleep₋₋ Enter bit ensures that processormodule 111a can execute critical sections of the power down sequencewithout any power-up reset signals arriving at processor module 111a.The S₋₋ Sleep₋₋ Enter bit provides an indicator to system controller 114that processor module 111a is in the process of being powered down andinhibits any attempt to power up processor module 111a until a secondsemaphore bit, the S₋₋ Wakeup₋₋ Enable bit, of system controller 114 isset by processor module 111a to indicate that module 111a has completedits power-down sequence and can now be powered-up. For a description ofthe configuration registers for implementing the sleep semaphores, and adescription of the inhibition of interrupts and data packets seeco-pending patent application, entitled "Packet Switched Cache CoherentMultiprocessor System", U.S. patent application Ser. No. 08/415,175,filed Mar. 31, 1995, assigned to Sun Microsystems, Inc.

Note that other implementations are possible. For example, as shown inFIG. 1F, in another embodiment of computer system 120, each module iscoupled to a distributed system controller and a distributed memory. Forexample, module 121a is coupled to distributed system controller 124aand distributed memory 125a. As such, processor modules of modules 121a. . . 121z can be individually powered down, with a separate semaphorebit pair, i.e., S₋₋ Sleep₋₋ Enter and S₋₋ Wakeup₋₋ Enable bits, providedfor each processor module.

Important state data of processor module 111a are then stored in stablememory, e.g., non-volative memory (step 230). The contents of localcache memory 111a1 are flushed into main memory 115 (step 240).Optionally, the contents of main memory 115 can be copied onto harddrive 194 if powering down of the DRAMs in main memory 115 is supported(step 245).

In this embodiment, one processor module, processor module 111a, isresponsible for initiating a power down of the shared resources ofcomputer system 110, e.g., peripheral devices such as disk drive 194 andgraphics display device 195 (step 250). For example, graphics controller119 may halt the vertical/horizontal synchronization signals and blankthe video signal to display device 195. Alternatively, display device195 can be powered down.

At this stage, the second semaphore bit, the S₋₋ Wakeup₋₋ Enable bit, isset (step 260). Setting the S₋₋ Wakeup₋₋ Enable bit provides anindicator that processor 111a has completed its power-down sequence.System controller 114 can now generate a reset signal to power upprocessor module 111a.

Finally, a ShutDown instruction is executed by processor module 111athereby completing the entry of computer system 110 into the sleep state(step 270). When a processor module, e.g., processor module 111a, ispowered-down, the internal clock of processor module 111a is disabled ina manner consistent with the underlying semiconductor technology. Forexample, in CMOS technology, it is advantageous to be able to stop theinternal processor clock to minimizing power consumption. In thisembodiment, when processor module 111a is powered-down, the main systemclock of computer system 110 remains running while the internalprocessor clock of processor module 111a is suppressed internally byprocessor module 111a.

In accordance with another aspect of the invention, when computer system110 is in the sleep state, computer system 110 appears to be awake withrespect to the other computer systems 120, . . . 170. This illusion ispossible because system controller 114, interconnect 112 and I/Ointerface module 111b remain powered-up. By remaining powered-up, I/Ointerface module 111b is continuously ready to receive data packets fromLAN 192. Hence, when a data packet arrives at I/O controller 118a fromLAN 192, I/O interface module 111b generates an Int₋₋ Req for systemcontroller 114, causing computer system 110 to enter the awake state.

In this implementation, data packets may be discarded at the networklevel, i.e., ignored by system controller 114. Although some networklevel packets may be lost, robust higher level protocols such as TCP maybe capable of recovering from such a loss without losing the networkconnection, thereby providing end-to-end integrity of data packetstransmitted by user applications executing on computer network 100. Thisadvantageous aspect of the present invention provides computer systems110, 120, . . . 170 with the illusion of appearing to be "awake" whileactually in the sleep state. In other implementations, the incoming datapackets are buffered at I/O interface module 111b until the intendedrecipient of the data packet, e.g., processor module 111a, has beenpowered up.

In accordance with another yet aspect of the invention, when computersystem 110 is in the sleep state, computer system 110 can be awakenunder pre-defined conditions called events. There are two classes ofevents; namely deterministic events and asynchronous events. Note thefollowing definitions of deterministic and asynchronous events areprovided to better illustrate the various events since the transition ofcomputer system 110 from the sleep state into the awake state inresponse to different events are similar.

Deterministic events are events triggered internally by computer system110. An example of a deterministic event is when computer system 110needs to execute a housekeeping chore such as a daily back up of thecontents of a hard drive onto magnetic tape, when an internal timerexpires, e.g., at midnight. Such an event is deterministic becausecomputer system 110 is the originator of the event and as such, controlsthe beginning and end of the housekeeping chore. Similarly, whenprocessor module 111a is the "write-enabled" owner of a data structurewhose most current copy is stored in local cache 111a1 of processormodule 111a, and a second processor module of computer system 110 needsto read and then write over the data structure, such a read of the datastructure initiated by the second processor module is also deterministicwith respect to computer system 110.

Conversely, asynchronous events are events triggered by a sourceexternal to computer system 110. An example of an asynchronous event isthe arrival of a network packet at network controller 118a and destinedfor a processor module of computer system 110. Another example of anasynchronous event is a user depressing a key on keyboard 196, ordepressing a standby button of computer system 110.

FIGS. 3A and 3B are flow diagrams illustrating the processing of anasynchronous event and a deterministic event, respectively. FIG. 3C is aflow diagram illustrating the wakeup sequence executed by computersystem 110 to transition from the sleep state into the awake state. FIG.4 shows an implementation of computer system 110 illustrating a pair ofreset signals for waking up computer system 110. The reset signals powerup any powered-down module(s) among modules 111a, 111c, . . . 111z whilepreserving the states of modules which remain powered-up, e.g., I/Ointerface module 111b. The two reset signals used by system controller114 are the UPA₋₋ Reset and UPA₋₋ Arb₋₋ Reset signals; the UPA₋₋ Arb₋₋Reset signal is provided to modules that are not powered down, e.g., I/Ointerface module 111b, while the UPA₋₋ Reset signal is provided topowered-down modules, e.g., processor module 111a and graphic module111z. In other implementations, where only selected processor modulesare powered down, the UPA₋₋ Arb₋₋ Reset signal is provided to processormodule(s) that remain powered-up.

Referring now to FIG. 3A, when computer system 110 detects anasynchronous event, e.g., the arrival of a network packet at I/O bus 116for powered-down processor module 111a (step 310), I/O bus 116 drops anyDMA request resulting from the asynchronous event (step 320). Acorresponding interrupt request (Int₋₋ Req) is generated by I/Ointerface module 111b for system controller (SC) 114 (step 325). Systemcontroller 114 NACKs (negative acknowledgment) the Int₋₋ Req from I/Ointerface module 111b (step 330). System controller 114 then sets theWakeup₋₋ Reset bit and also asserts a Reset₋₋ Call bit to initiate awakeup sequence for computer system 110 (step 340). Meanwhile, I/Ointerface module 111b keeps resending Int₋₋ Req to SC 114 (step350). SC114 responds by reNACKing (step 370) until computer system 110 hascompleted the wakeup sequence (step 360). In this implementation, theI/O₋₋ Wakeup₋₋ Enable bit is cleared to indicate that the processormodule(s) of computer system 110 are now powered-up, e.g., processormodule 111a is now powered up and is able process to the cause of theInt₋₋ Req. For a detailed description of the reset signals and theACK/NACK protocol, see co-pending patent application, entitled "PacketSwitched Cache Coherent Multiprocessor System", U.S. patent applicationSer. No. 08/415,175, filed Mar. 31, 1995, assigned to Sun Microsystems,Inc.

Upon completion of the wakeup sequence, system controller 114 sends anACK to I/O interface module 111b and a corresponding interrupt packet toprocessor module 111a (step 380). Processor module 111a is nowpowered-up and able to handle the interrupt packet from SC 114 (step390). Computer system 110 is now in the awake state.

As shown in FIG. 3B, when computer system 110 detects a deterministicevent, e.g., expiration of a timer, an Int₋₋ Req is generated for systemcontroller 114 (step 322). System controller 114 NACKs the Int₋₋ Req(step 332). Next, system controller 114 sets the Wakeup₋₋ Reset bit, andalso asserts the Reset₋₋ Call bit to initiates a wakeup sequence forcomputer system 110 (step 340). Upon completion of the wakeup sequence(step 360), system controller sends a corresponding interrupt packet toprocessor module 111a (step 382). Processor module 111a is powered-upand able to handle the interrupt packet, e.g., attend to the expirationof the timer (step 392). Computer system 110 is now in the awake state.

Referring now to FIG. 3C, the wakeup sequence of computer system 110 isdescribed in greater detail. In this embodiment, reset signals are sentto processor module 111a in the following manner. First, systemcontroller 114 asserts a request to become a master of system bus 490(FIG.4). When system controller 114 is granted system bus 490, SC 114asserts the UPA₋₋ Arb₋₋ Reset signal for powered-up module(s), and UPA₋₋Reset signal for powered-down module(s), e.g., I/O interface module 111band processor module 111a, respectively (step 341). The UPA₋₋ Arb₋₋Reset signal allows the powered-up modules to synchronize their internalarbitration state(s) i.e., selectively clear arbitration state(s),without completely clearing all its internal states. System controller114 holds the UPA₋₋ Arb₋₋ Reset signal low for the same duration asUPA₋₋ Reset signal. Note that before de-asserting the UPA₋₋ Arb₋₋ Resetsignal, SC 114 de-asserts its request for system bus 490, and resets itsown internal arbitration state to update the respective status bits ofprocessor modules 111a, 111c.

Next, processor module 111a executes a power-up boot sequence (step342). The boot sequence code is located in a suitable non-volatilememory such as in a boot PROM.

The Wakeup₋₋ Reset bit in system controller 114 is then polled todetermine the cause of the reset signals (step 343). When a powered-downmodule of computer system 110, e.g., processor module 111a, is providedthe UPA₋₋ Reset signal, module 111a is unaware of the origin or cause ofthe reset signal, i.e., whether the UPA₋₋ Reset signal was caused by awakeup sequence or by a system-wide power-up sequence of computer system110. Hence, if the Wakeup₋₋ Reset bit is not set, computer system 110executes a system-wide power-up sequence (step 345). Conversely, if theWakeup₋₋ Reset bit is set, computer system 110 proceed with theexecution of the wakeup sequence.

Upon determining that the cause was a wakeup of computer system 110,power is restored to any powered-down shared resources such asperipheral devices (step 346). Important data is restored from thestable memory (step 347). Finally, the S₋₋ Sleep₋₋ Enter, S₋₋ Wakeup₋₋Enable and Wakeup₋₋ Reset bits of system controller 114 are cleared(step 348), together with the I/O Wakeup₋₋ Enable control bit of I/Ointerface module 111b (step 349), thereby indicating that computersystem 110 has completed its wakeup sequence. The order of clearing thecontrol and semaphore bits is important so as to enable processor module111a to distinguish between a power-up reset or a system-wide power-onreset. Computer system 110 is now in the awake state and processormodule 111a is ready to process the cause of the event.

In some embodiments of computer system 110, addition states areprovided, e.g., a "suspend" state, a "standby" state. The suspend statehas a lower level of readiness than that of the sleep state. In thesuspend state, computer system 110 is not network available, i.e., itappears to be sleeping with respect to the rest of computer network 100.The main power supply of computer system 110 is in a low power "standby"mode. A backup battery provides power to an alarm timer for wakingcomputer system 110. Upon expiration of the alarm timer, the main powersupply is re-enabled which wakes computer system 110 up. In addition,depressing a "power" key on keyboard 196 or a main on/off power switchalso restarts computer system 110. The suspend state is useful forcomputer systems that need not be "network alive", i.e., appear awakeall the time.

The standby state of computer system 110 has a readiness level betweenthat of the sleep state and the awake state. In the standby state, allprocessor modules remain awake while inactive peripheral devices, e.g.,disk drive(s) and display device(s) are turned off or enter a low powermode.

Other modifications and additions are possible without departing fromthe spirit of the invention. For example, the total number of processormodules within each computer system can be smaller or larger. Inaddition, the control functions provided by the system controller ofeach computer system can be distributed among the modules of eachcomputer system. Other computer network configurations and hybrids ofprocessor modules are also possible. For example, clusters ofmulti-module computer systems may be coupled to each other by a varietyof means including high speed buses. It is also possible for someprocessor modules to remain continuously powered up, and/or for some I/Ointerface modules which only control passive devices such as magnetictape drives and laser disk drives to be powered down. Hence the scope ofthe invention should be determined by the following claims.

What is claimed is:
 1. A method for managing power in a computer networkhaving a plurality of computer systems and a network connection means,each said computer system including a processor module, an input/output(I/O) interface module and a main memory, each said I/O interface modulecoupled to the network connection means, the method comprising the stepsof:setting an indicator corresponding to a first said processor moduleof a first computer system to indicate a power down of the firstprocessor module corresponding to a transition of the first computersystem from an awake state into a sleep state; storing data includingstate information of the first processor module in a first said mainmemory of the first computer system; powering down the first processormodule while a first said I/O interface module of the first computersystem remains powered up, thereby reducing the power consumption of thecomputer network; detecting an asynchronous event initiated by a sourceexternal to the first computer system; and responding to the detectionof the asynchronous event by:powering up the first processor module andperforming a wake-up sequence in the processor module; generating,within the first computer system, an interrupt request corresponding tothe asynchronous event and regenerating the interrupt request until apositive acknowledgement of the interrupt request is generated; andresponding to each interrupt request corresponding to the asynchronousevent by (A) generating a negative acknowledgment of the interruptrequest if the first processor module has not completed the wake-upsequence, and (B) generating a positive acknowledgement of the interruptrequest and sending to the first processor module an interrupt packetcorresponding to the asynchronous event if the first processor modulehas completed the wake-up sequence.
 2. The method of claim 1, whereinthepowering down step includes performing a powering down sequence, whereina beginning portion of the powering down sequence includes setting aSleep Entered status bit and an ending portion of the powering downsequence includes setting a Wakeup Enable bit; at completion of thewake-up sequence of the first processor module, clearing the SleepEntered status bit and the Wakeup Enabled bit; wherein whenever theSleep Entered bit is set and the Wakeup Enable bit is clear, powering upof the first processor module is inhibited until the powering downsequence is completed.
 3. The method of claim 1, wherein the step ofperforming a wake-up sequence includes:executing a boot sequence withthe first processor module; and restoring data including the stateinformation of the first processor module from the first main memory. 4.The method of claim 3 wherein the asynchronous event is a network packetarriving at the first I/O interface module.
 5. The method of claim 1further comprising the step of sending an arbitration reset signal tothe first I/O interface module which selectively resets an arbitrationstate of the first I/O interface module.
 6. A computer systemcomprising:a processor module, including means for executing a powerdown sequence and for executing a wake-up sequence; an input/output(I/O) interface module coupled to a network connection means forreceiving network packets and detecting asynchronous events initiated bysources external to the computer system; a main memory for storing dataincluding state information of the processor module; and a systemcontroller coupled to the I/O interface module and the processor module;the power down sequence including storing data including stateinformation of the processor module in the main memory and powering downthe processor module while the I/O interface module remains powered up;the I/O interface module including means for responding to detection ofthe asynchronous event by sending an interrupt request to the systemcontroller, and for regenerating the interrupt request until a positiveacknowledgment of the interrupt request is received; the systemcontroller including means for responding to a first interrupt requestcorresponding to the asynchronous event by causing the processor moduleto power up and start executing the wake-up sequence, and for respondingto each interrupt request corresponding to the asynchronous event by (A)sending the I/O interface module a negative acknowledgment of theinterrupt request if the processor module has not completed the wake-upsequence, and (B) generating a positive acknowledgement of the interruptrequest and sending to the processor module an interrupt packetcorresponding to the asynchronous event if the processor module hascompleted the wake-up sequence.
 7. The computer system of claim 6whereinthe system controller's means for responding to the firstinterrupt request includes means for setting a Sleep Entered status bit,and the system controller's means for responding to each interruptrequest when the processor module has completed the wake-up sequenceincludes clearing the Sleep Entered status bit; the power down sequenceincluding setting a Wakeup Enabled bit at an ending portion of thepowering down sequence; the wake-up sequence includes clearing theWakeup Enabled bit at completion of the wake-up sequence; whereinwhenever the Sleep Entered bit is set and the Wakeup Enabled bit isclear, powering up of the processor module is inhibited until thepowering down sequence is completed.
 8. The computer system of claim 7wherein the wake-up sequence includes:executing a boot sequence with theprocessor module; and restoring data including the state information ofthe processor module from the main memory.
 9. The computer system ofclaim 8 wherein the asynchronous event is a network packet arriving atthe I/O interface module.
 10. A method for managing power in a computernetwork having a plurality of computer systems and a network connectionmeans, each said computer system including a processor module, aninput/output (I/O) interface module and a main memory, each I/Ointerface module coupled to the network connection means, the methodcomprising the steps of:performing a powering down sequence in a firstone of the computer systems to transition the first computer system froman awake state into a sleep state, including:storing data includingstate information of the first processor module in a first said mainmemory of the first computer system; and powering down the firstprocessor module while a first said I/O interface module of the firstcomputer system remains powered up, thereby reducing the powerconsumption of the computer network; detecting an asynchronous eventinitiated by a source external to the first computer system; andresponding to the detection of the asynchronous event by:powering up thefirst processor module and performing a wake-up sequence in the firstprocessor module; generating, within the first computer system, aninternal interrupt request corresponding to the asynchronous event andregenerating the interrupt request whenever a negative acknowledgment ofthe interrupt request is generated; and responding to each interruptrequest corresponding to the asynchronous event by (A) generating anegative acknowledgment of the interrupt request if the first processormodule has not completed the wake-up sequence, and (B) generating apositive acknowledgment of the interrupt request and sending to thefirst processor module an interrupt packet corresponding to theasynchronous event if the first processor module has completed thewake-up sequence.
 11. The method of claim 10, whereinthe powering downstep includes performing a powering down sequence, wherein a beginningportion of the powering down sequence includes setting a Sleep Enteredstatus bit and an ending portion of the powering down sequence includessetting a Wakeup Enabled bit; at completion of the wake-up sequence ofthe first processor module, clearing the Sleep Entered status bit andthe Wakeup Enabled bit; wherein whenever the Sleep Entered bit is setand the Wakeup Enabled bit is clear, powering up of the first processormodule is inhibited until the powering down sequence is completed. 12.The method of claim 10, the step of performing a wake-up sequenceincluding:executing a boot sequence with the first processor module; andrestoring data including the state information of the first processormodule from the first main memory.
 13. The method of claim 10, whereinthe asynchronous event is a network packet arriving at the first I/Ointerface module.
 14. A computer system comprising:a processor module,including means for executing a power down sequence and for executing awake-up sequence; an input/output (I/O) interface module coupled to anetwork connection means for receiving network packets and detectingasynchronous events initiated by sources external to the computersystem; a main memory for storing data including state information ofthe processor module; and a system controller coupled to the I/Ointerface module and the processor module; the power down sequenceincluding storing data including state information of the processormodule in the main memory and powering down the processor module whilethe I/O interface module remains powered up; the I/O interface moduleincluding means for responding to detection of an asynchronous event bysending an interrupt request to the system controller, and forregenerating the interrupt request whenever a negative acknowledgment ofthe interrupt request is received; the system controller including meansfor responding to a first interrupt request corresponding to theasynchronous event by causing the processor module to power up and startexecuting the wake-up sequence, and for responding to each interruptrequest corresponding to the asynchronous event by (A) sending the I/Ointerface module a negative acknowledgment of the interrupt request ifthe processor module has not completed the wake-up sequence, and (B)generating a positive acknowledgment of the interrupt request andsending to the processor module an interrupt packet corresponding to theasynchronous event if the processor module has completed the wake-upsequence.
 15. The computer system of claim 14, wherein:the systemcontroller's means for responding to the first interrupt requestincludes means for setting a Sleep Entered status bit, and the systemcontroller's means for responding to each interrupt request when theprocessor module has completed the wake-up sequence includes clearingthe Sleep Entered status bit; the power down sequence includes setting aWakeup Enabled bit at an ending portion of the powering down sequence;the wake-up sequence includes clearing the Wakeup Enabled bit atcompletion of the wake-up sequence; wherein whenever the Sleep Enteredbit is set and the Wakeup Enabled bit is clear, powering up of theprocessor module is inhibited until the powering down sequence iscompleted.
 16. The computer system of claim 14, wherein the wake-upsequence includes:executing a boot sequence with the processor module;and restoring data including the state information of the processormodule from the main memory.
 17. The computer system of claim 14 whereinthe asynchronous event is a network packet arriving at the I/O interfacemodule.